Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
In a conventional deficit round robin (DRR) scheduling, a packet processor processes data packets from a plurality of traffic flows or queues. Each queue is assigned a corresponding weight based on, for example, a priority of the queue. In each DRR cycle, a counter associated with a queue is incremented by the assigned weight of the queue. During a DRR cycle, a size of a packet to be processed from a queue is compared with the associated counter. If the size of the packet in the queue is greater than the associated counter, the packet is not processed in that DRR cycle (e.g., the processing of the packet is carried forward for a future DRR cycle). However, if the counter is at least as high as the size of the packet, the packet is processed during the DRR cycle and the counter is updated by subtracting the packet size from the previous counter value.
If the sizes of the packets in the queues are relatively large compared to the respective weights of the queues, in a conventional DRR scheduling, no packets may be processed during several DRR cycles. That is, several DRR cycles are wasted (e.g., wasted as no packet processing occurs during these DRR cycles), as the counters are not high enough to allow processing of the data packets. These wasted DRR cycles in a conventional packet processing system generally results in performance degradation of the system.